HBM5 targets: 2× bandwidth, better perf/W
At its Memory Executive Summit, Samsung outlined its goals for next‑gen HBM5 memory:
- 2× the performance of HBM4E per stack
- Around 20% higher performance per watt
Samsung also confirmed that HBM5 stacks will integrate a heat path block (HPB), expected to cut thermal resistance by ~20%, simplifying cooling for dense HBM packages.
If per‑stack bandwidth is doubled, HBM5 would reach roughly 4 TB/s per stack in the 2028–2029 timeframe.
4,096‑bit interface on the table
Today, DRAM vendors and IP providers already ship HBM4/HBM4E PHYs and controllers capable of 16 GT/s, but the JEDEC official data rate for HBM4E is expected to be about 12 GT/s.
To get 2× HBM4E bandwidth, the HBM5 spec must do at least one of the following:
- Double per‑pin data rate from 12 GT/s → 24 GT/s
- Double interface width from 2,048 → 4,096 bits
- Use a mix of wider bus + higher speed
A 4,096‑bit HBM interface has already been explored by KAIST and Marvell, but there is no semi‑official confirmation that JEDEC will adopt it.
From a performance‑per‑watt perspective, widening the interface is usually easier than pushing per‑pin speeds well beyond 20 GT/s, which demands faster drivers/receivers, tighter timing, stronger equalization, and a more complex PHY. However, going from 2,048 to 4,096 I/Os doubles TSVs, bumps, routing complexity, and makes the base die extremely challenging.
A compromise such as a 3,072‑bit bus with a moderate speed bump might be more practical, but for now all concrete HBM5 details remain speculative.
Meanwhile, TSMC expects AI accelerators to integrate 20–24 HBM5/HBM5E stacks per package by the end of the decade, yielding a staggering 80–96 TB/s of aggregate memory bandwidth.
The ambition to double HBM4E’s 2 TB/s per‑stack bandwidth in a single generation underlines how aggressively memory is scaling to keep up with AI workloads.
Source: Tom's Hardware
