IBM has announced the world’s first sub-1 nanometer chip technology, demonstrating an experimental device at the 0.7 nm (7 angstrom) node. The prototype packs roughly 100 billion transistors into an area the size of a fingernail, nearly double the density of IBM’s 2 nm node revealed in 2021.
Beyond nanometers: entering the atomic scale
At the heart of this breakthrough is a completely new transistor architecture called "nanostack" – the industry’s first known three-dimensional, nanosheet-based design:
- transistors are vertically stacked and staggered in 3D;
- 3D sequential integration enables much higher device density;
- each stacked layer can use different material combinations, allowing independent optimization of performance and power for each transistor.
According to IBM’s published projections, chips built on this 0.7 nm node could deliver up to 50% higher performance or up to 70% better energy efficiency compared to its 2 nm technology. That kind of gain directly benefits generative AI, cloud infrastructure, and next‑generation consumer and industrial electronics.
How IBM validated the nanostack concept
IBM researchers experimentally validated the nanostack architecture through several key milestones:
- ultra-thin dielectric bonding in a CMOS integration flow;
- demonstration of dual-channel engineering capability;
- a functional CMOS inverter with switching behavior matching expectations.
Together, these results show that nanostack is not just a theoretical idea but a physically realizable technology that can support real computation in CMOS logic. For the semiconductor industry, this points to a path beyond the traditional nanometer era, down to atomic‑scale features, potentially reshaping everything from high‑end servers to low‑power embedded devices in the coming decade.
Source: newsroom.ibm.com
